# ExpertX > ExpertX runs two practices: an engineering studio for board-level hardware, firmware, PCB, manufacturing, and NPI packaging and test, and an origination practice that sources, structures, and executes complex B2B deals. ExpertX is based in Santa Clara, CA. Contact: hello@expertx.net. ## Engineering From first silicon to shipped board. Hardware engineering for teams who can't afford a re-spin. We package and qualify first silicon, then design, lay out, and manufacture the board around it — high-speed digital, RF, mixed-signal, power — and own the path from prototype through production. ### [Hardware Engineering](https://www.expertx.net/services/hardware-engineering) Board-level design for systems where signal integrity, power, and thermals are non-negotiable. We work with teams shipping into demanding environments — semiconductors, defense, industrial, medical — and the work assumes that environment from the first schematic, not the last design review. Every engagement covers the analysis the board actually needs: signal integrity, power integrity, EMC, thermal, and DFM. Compliance scope (CE, FCC, RoHS) is scoped in up front so it doesn't surface as rework at the end. - High-speed digital: DDR4 / DDR5 memory interfaces; PCIe Gen 3 / 4 / 5; USB 3.x; HDMI, DisplayPort; Multi-gigabit Ethernet - RF & microwave: DC to 100+ GHz circuit design; Antenna design and matching networks; Filters, amplifiers, RF front-ends; Cellular, Wi-Fi, Bluetooth, custom RF - Mixed-signal & analog: Precision data acquisition; Sensor interfaces; Low-noise amplification; ADC / DAC integration - Power & integrity: Power supply and power management design; High-power and high-temperature applications; Signal and power integrity analysis; EMC design, thermal analysis; Design for manufacturability (DFM) ### [Firmware & Embedded Systems](https://www.expertx.net/services/firmware-embedded) Bare-metal and RTOS firmware on ARM, RISC-V, and Espressif — from board bring-up to OTA. Firmware that has to run for years in the field, not just demo on the bench. We write drivers, integrate wireless stacks, and stand up bootloaders with secure update paths so the device on the shelf can be fixed in the field. Board bring-up is part of the practice — first prototype to functional firmware in days, with the hardware/firmware integration debugging that prototype phase always actually needs. - Runtimes: Bare-metal development; FreeRTOS, Zephyr, ThreadX; Low-power and battery-operated systems; Real-time control systems - Platforms: ARM Cortex-M — STM32, NXP, Nordic, TI; ARM Cortex-A — i.MX, Raspberry Pi; RISC-V — SiFive, ESP32-C3; Espressif — ESP32, ESP8266; Microchip PIC and AVR - Connectivity & drivers: I²C, SPI, UART, USB, Ethernet drivers; BLE 4.x / 5.x, Wi-Fi, Zigbee; LoRa, LTE-M, NB-IoT; Custom RF protocol stacks - Reliability & security: Bootloaders and OTA firmware update; Sensor fusion and data processing; Security and cryptography implementation; Board bring-up and hardware validation ### [PCB Design & Layout](https://www.expertx.net/services/pcb-design-layout) Two to seventy-six layers, including HDI, flex, rigid-flex, and high-speed — with SI/PI built into the routing, not bolted on at the end. PCB layout is where most boards quietly fail — signal integrity that simulates fine but fabricates poorly, stackups that look reasonable but are uneconomic to build, footprints that pass DRC and fail assembly. We treat layout as a real engineering discipline, not a CAD task. Signal-integrity and power-integrity analysis run alongside the layout, not as a final check. Critical signals get verified against timing and quality requirements before fabrication, on the schedule the layout is on. - Layout scope: Multilayer PCB design — 1 to 76 layers; HDI with microvias and blind / buried vias; High-speed routing and impedance control; RF and microwave PCB layout; Flex and rigid-flex - Analysis: Signal integrity (HyperLynx, ADS); Power integrity; 3D field solvers (CST, HFSS); Pre-fab verification of critical signals - Design tools: Altium Designer; Cadence Allegro; PADS Professional; KiCad - Deliverables: DFM-optimized layouts; 3D modeling and mechanical integration; Component selection and sourcing support; Full design documentation and fab files ### [Manufacturing & Assembly](https://www.expertx.net/services/manufacturing-assembly) Prototype to production, SMT and through-hole, with sourcing and quality systems in the same engagement. Prototype fabrication on a turn that lets design iterate, and production runs that hold the same quality from the first hundred boards to the ten-thousandth. Both motions run through the same engineering team, so the design notes don't get lost at the handoff to fab. Sourcing, inventory, and JIT delivery are part of the service — not a separate vendor the customer has to manage. Quality systems and traceability are built in so audits, recalls, and regulated industries are practical, not painful. - Fabrication: Quick-turn prototypes; Production manufacturing — low to high volume; Multilayer, HDI, flex, rigid-flex - Assembly: Surface-mount (SMT) assembly; Through-hole assembly; Box build and final assembly - Sourcing & logistics: Component sourcing and procurement; Inventory management and JIT delivery; Turnkey services across design, fab, and assembly - Quality: DFM analysis pre-build; Inspection and testing programs; Full traceability for regulated industries ### [Packaging, Test & Failure Analysis](https://www.expertx.net/services/packaging-test) Quick-turn packaging, reliability qualification, and failure analysis built for NPI: one team from first silicon to a qualified part on a working board. New product introduction is where packaging, test, and board design usually live with three different vendors, and the schedule dies in the handoffs between them. We run all three on one team. Die comes in, gets packaged, qualified, and debugged, and lands on a board we designed for it, without anyone re-explaining the part at each step. Silicon has to get into a package before it can go on a board, and that step is where small-batch programs stall. Engineering samples, MPW shuttle die, and MEMS parts rarely justify a production slot at a large assembly house, but they still need the right package on a schedule measured in days, not quarters. We cover the post-fab path at prototype and small-batch volumes: wafer thinning and dicing, quick-turn ceramic and plastic packaging, reliability qualification, electrical test, and failure analysis when a part doesn't behave. Because the board team is in the room, the package gets picked with the footprint, thermals, and assembly already in view. - Quick-turn packaging: Ceramic: DIP, QFP, SOP, QFN, LCC, PGA, SiP, BGA; Plastic: DIP, LQFP, QFN, DFN, SOP, SSOP, TSSOP, SOT, TO, BGA; Chip-on-board (COB) bonding; BGA, LGA, and multi-die stacked packages; MEMS sensor and optical device packages; LCD driver IC bonding - Wafer services: MPW and shuttle die handling, block and 5×5; 6 to 12 inch wafer thinning and dicing; GaAs thinning and dicing; Automated bare-die pick and sort, vacuum packing - Substrates: High-speed BGA substrate design and simulation; Substrate fabrication and processing - Reliability qualification: HTOL, HTRB, HTGB, H3TRB; THB, HAST, PCT, TCT, THST, THCT; HTST, LTST, BLT; MSL preconditioning and reflow; Burn-in boards and DUT cards - Electrical test: ESD: HBM, MM, CDM; Latch-up; Wafer probe (CP) and final test (FT) - Failure analysis & circuit edit: FIB circuit edit down to 28nm; Chemical and physical decap, die extraction, delayering; SEM imaging from 50× to 200,000×; Backside FA sample prep and defect localization; Competitive teardown analysis - Rework & custom hardware: Post-decap re-bonding, wire removal, and jumpers; BGA reballing, re-soldering, dispensing, and molding; MEMS housings with windows and special ceramic packages; Custom test fixtures - Quality systems: Packaging and test performed in ISO 9001, ISO 14001, and ISO 45001-certified facilities. Certificates available under NDA. ## Packaging & test in depth ### [Quick-Turn Ceramic Packaging](https://www.expertx.net/services/packaging-test/ceramic-packaging) Small-batch ceramic DIP, QFP, QFN, LCC, PGA, SiP, and BGA packages for engineering samples, MPW die, and parts that need to survive characterization. Ceramic is the default for first silicon that has to be characterized hard: it runs hotter, seals better, and opens cleanly when a part needs to come back out for failure analysis. The catch is that production ceramic lines aren't set up for twenty parts. We package ceramic in small batches, from a handful of MPW die to a pilot lot, and quote per die and drawing. Cavity, lid, bond plan, and pinout are worked out against the board the part is going onto, so the first package is one the board team can actually use. - Package families: Ceramic DIP and SOP; Ceramic QFP and QFN; LCC (leadless chip carrier); PGA (pin grid array); Ceramic BGA and SiP - Specialty builds: Chip-on-board (COB) bonding; Multi-die stacked packages; MEMS sensor and optical packages, including housings with windows; Special and custom ceramic packages to drawing; LCD driver IC bonding - Wafer prep in the same flow: MPW and shuttle die handling, block and 5×5; Wafer thinning and dicing, including GaAs; Automated bare-die pick and sort Ceramic & COB catalog (Package | Pins | Body size): - Ceramic QFP | 64–256 | 10×10 to 28×28 mm - Ceramic DIP | 8–64 | 300, 600, 900 mil - Open-cavity QFN | 16–100 | 2×2 to 12×12 mm - Ceramic SOP | 16, 24 | Standard - Ceramic PGA | 84, 100, 132, 256 | Standard - Ceramic LCC | 28, 48, 64, 84 | Standard - Ceramic BGA | To drawing | To drawing - COB | 48, 64, 256, 1,024, or to drawing | To drawing FAQ: - Q: What's the minimum quantity for ceramic packaging? A: There isn't a production-style minimum. Ceramic builds are quoted per die and drawing, and engineering-sample quantities are the normal case. - Q: Can you package die from an MPW shuttle? A: Yes. We handle MPW and shuttle die, including block and 5×5 formats, and can thin, dice, and sort before packaging. - Q: When should I pick ceramic over plastic for first silicon? A: Ceramic suits characterization at temperature, hermetic needs, and parts likely to need decap and failure analysis. Plastic is closer to the production package and cheaper per unit. Many NPI programs do both. ### [Quick-Turn Plastic Packaging](https://www.expertx.net/services/packaging-test/plastic-packaging) Small-batch molded packages from 3-pin SOT to 256-pin LQFP, so engineering samples ship in the package production will use. Testing first silicon in the package it will ship in catches the problems a ceramic sample hides: mold stress, wire sweep, thermal paths that only exist in plastic. Large assembly houses rarely want a lot that small. We run quick-turn plastic packaging at prototype and pilot volumes across the standard families below. Bring the die and the target package and we'll confirm the bond plan. Because the board team is on the same engagement, footprint and thermal pad questions get answered before the part is molded. - Package families: QFN and DFN; LQFP, plus eLQFP / HLQFP with heat slug; SOP, SSOP, TSSOP, MSOP, eSOP; DIP; SOT and TO power packages; Plastic BGA - Around the package: Wafer thinning, dicing, and die sort; MSL preconditioning and reflow; Final test (FT) BGA, LGA, SiP & MEMS (Family | Spec | Range): - BGA | Body size | 2×2 to 29×29 mm - BGA | Mold thickness | 0.55 to 1.5 mm - BGA | Balls and pitch | From 0.2 mm balls at 0.4 mm pitch - LGA | Body size | 2×2 to 20×12 mm - LGA | Mold thickness | 0.55 to 1.5 mm - SiP | Configurations | Side by side, stacked die, IC plus passives - SiP | Assembly | Wire bond, flip chip, and SMT in one package - Bumping | Ball attach | Single die and wafers up to 6 in; balls from 60 µm - MEMS | Package style | Open-cavity or windowed; windows from 0.6 mm FAQ: - Q: What plastic packages can you build in small batches? A: QFN, DFN, LQFP (including heat-slug variants), SOP, SSOP, TSSOP, MSOP, eSOP, DIP, SOT, TO, and BGA. Pin counts and body sizes are listed in the catalog on this page. - Q: Do you support exposed-pad and heat-slug packages? A: Yes. eLQFP / HLQFP in 80, 128, 144, and 176 pins, and eSOP in 8 and 28 pins. - Q: Can the same team design the board the part goes on? A: Yes. That's the point of running packaging inside an engineering studio: the package, footprint, and board are decided together. ### [Reliability Qualification & Electrical Test](https://www.expertx.net/services/packaging-test/reliability-qualification) HTOL, HAST, THB, temperature cycling, ESD, and latch-up for new parts, plus the burn-in boards and DUT cards to run them. Qualification is where NPI schedules slip quietly. The test plan is fine; what's missing is the burn-in board, the socket, or a lab slot that lines up with when parts come off the packaging line. We run qualification on the same engagement as packaging, so parts move straight from assembly into stress, and the burn-in boards and DUT cards come with it. When something fails, failure analysis is part of the same engagement rather than another purchase order. - Life & bias stress: HTOL: high-temperature operating life; HTRB / HTGB: high-temperature reverse and gate bias; H3TRB: high-humidity, high-temperature reverse bias; BLT: bias life test - Environmental stress: HAST: highly accelerated stress test; THB: temperature-humidity bias; PCT: pressure cooker test; TCT: temperature cycling; THST / THCT: thermal shock and thermal cycling variants; HTST / LTST: high- and low-temperature storage - Assembly robustness: MSL preconditioning, levels 1 to 6; Reflow simulation - Electrical test: ESD: HBM, MM, CDM; Latch-up; Wafer probe (CP); Final test (FT) - Burn-in boards: HTOL, THB, HAST, H3TRB, HTGB, and HTRB boards; Turnkey: schematic, layout, SMT, and debug; High-Tg, polyimide, and FR4 materials; Board count sized from sockets, power, and per-pin current; DUT cards and custom test fixtures FAQ: - Q: Which reliability tests do you run? A: HTOL, HTRB, HTGB, H3TRB, BLT, HAST, THB, PCT, TCT, THST, THCT, HTST, LTST, MSL preconditioning, and reflow, plus ESD (HBM, MM, CDM) and latch-up. - Q: Do you provide burn-in boards? A: Yes, turnkey: we size the sockets and board count from your schematic and package drawing, then design, lay out, assemble, and debug the boards. That removes the most common wait in a qualification schedule. - Q: Can you package and qualify the same lot? A: Yes. Packaging, qualification, and failure analysis run on one engagement, so parts move from assembly into stress without a handoff. ### [Failure Analysis & FIB Circuit Edit](https://www.expertx.net/services/packaging-test/failure-analysis-fib) FIB circuit edit down to 28nm, decap, delayering, and SEM imaging, so a first-silicon bug can be proven and patched before the next tape-out. When first silicon doesn't behave, the expensive question is whether the fix needs a new mask set. FIB circuit edit answers it: cut and reroute metal on the actual die, prove the fix on the bench, and only then commit to a re-spin. Failure analysis runs alongside it. We decap, delayer, and image down to the defect, and because the same team packaged the part and designed the board, the analysis starts with the full history instead of a box of returned units. - Circuit edit: FIB circuit edit down to the 28nm node; Metal cuts and reroutes on the actual die - Failure analysis: Chemical and physical decap; Die extraction and delayering; SEM imaging from 50× to 200,000×; Backside FA sample prep; Hot-spot localization by photon emission (EMMI); Cross-sections, TEM sample prep, voltage contrast; Remarking - Post-decap rework: Re-bonding, wire removal, and jumpers; Re-soldering and BGA reballing; Dispensing and re-molding - Competitive analysis: Teardown and construction analysis of third-party parts FIB metal resistance (Metal | Bulk | CVD | FIB line | FIB contact): - Tungsten (W) | 0.05 | 0.2 | 3 | 70 - Platinum (Pt) | 0.1 | 0.5 | 7 | 140 FAQ: - Q: What's the smallest node you can FIB edit? A: Circuit edit is supported down to the 28nm node. - Q: Can you rebond or repackage a part after decap? A: Yes. Post-decap rework covers re-bonding, wire removal, jumpers, re-soldering, BGA reballing, dispensing, and re-molding. - Q: Do you do competitive teardown? A: Yes. Teardown and construction analysis of third-party parts is part of the failure-analysis practice. ### [Package & Substrate Design](https://www.expertx.net/services/packaging-test/package-substrate-design) Package selection, substrate stack-up, ball maps, and SI, PI, and thermal co-simulation for flip-chip BGA, SiP, and chiplet designs. Above a few hundred balls, the package stops being a container and becomes a circuit. Stack-up, ball map, and power delivery decide whether the DDR and SerDes links close, and they're cheapest to fix before the substrate is built. We design the package and substrate alongside the die and the board: package and material selection, stack-up, ball map, impedance, and substrate layout, checked with chip-package-substrate co-simulation. The same team designs the board it lands on, so the ball map is planned against the breakout. - Custom design: Package selection; Substrate and material selection; Stack-up and ball-map design; Impedance design; Substrate layout - Simulation: Power and ground, DC and AC; High-speed and system-level channel simulation; Thermal performance; Structural design and stress; EMI, SI, and PI co-optimization - Advanced integration: System-in-package: side by side, stacked die, IC plus passives; Wire bond, flip chip, and SMT in one package; TSV 2.5D interposer design; Chiplet-based micro-systems and heterogeneous integration; DDR3 and Flash wafer-level packaging with bumping - Substrates: High-speed BGA substrate design and fabrication; Organic substrates, BT and ABF build-up; Multilayer ceramic substrates Representative builds (Build | Package and substrate | Size and balls | Key interfaces): - CPU + FPGA network processor | HFcBGA, 10-layer organic | 61×61 mm, 3,576 balls | DDR3 1,600 Mbps, PCIe 2.0, XAUI 6.25 Gbps - CPU + FPGA + Flash SiP | HFcBGA, 10-layer organic | 50×50 mm, 2,089 balls | PCIe x16 3.0, DDR3 x72, USB 2.0 - Integrated DSP module | HFcBGA, 10-layer organic | 35×35 mm, 1,024 balls | 4×72-bit DDR3, PCIe 3.0, 10.125 Gbps SerDes, 60 W, 8 GB DDR4 inside - AI chip for healthcare | fcBGA, 10-layer organic | 23×23 mm, 529 balls | LPDDR4 at 4,266 MHz - Fibre Channel switch | fcBGA, 6-layer organic | 19×19 mm, 529 balls | Multiple 12.5 Gbps SerDes - Mixed-signal RF transceiver SoC | fcBGA, 8-layer ABF build-up | 15×15 mm, 289 balls | 16 Gbps SerDes, 1.5 GHz ADC input - AD/DA SiP | BGA, 6-layer BT | 27×27 mm, 636 balls | 3-tier gold-wire fan-out, 1 digital + 4 ADC + 1 DAC + Flash - Health-monitoring SiP | Package-on-package, 4-layer organic | 18×18 mm, 393 balls | Copper-core-ball interposer, several mixed-signal die FAQ: - Q: Can you design the substrate if we only have the die? A: Yes. Package selection, stack-up, ball map, and substrate layout start from the die pad map and the board it has to land on. - Q: Do you simulate before the substrate is built? A: Yes. Chip, package, and substrate are co-simulated for signal integrity, power integrity, thermal behavior, and structural stress. - Q: Do you do SiP and chiplet designs? A: Yes: side-by-side and stacked-die SiP, IC plus passives, mixed wire bond, flip chip, and SMT, plus TSV 2.5D interposer and chiplet-based designs. ### [Wafer Thinning, Dicing & Die Sort](https://www.expertx.net/services/packaging-test/wafer-thinning-dicing) Thinning to 50 µm, laser and blade dicing, SiC stealth dicing, GaAs laser dicing, and automated die sort for MPW, shuttle, and full wafers. Most quick-turn packaging starts before the package. An MPW shuttle comes back as a wafer shared with other designs, and your die have to be thinned, cut out, and sorted before anyone can bond them. We thin and dice wafers from 2 to 12 inches, cut MPW and shuttle wafers by block, and sort die by ink or wafer map into trays or wafer frames. The die go straight into packaging on the same engagement. - Thinning: Wafers from 2 to 12 in, plus bare die, blocks, and MPW; 8 and 12 in: down to 50 µm without bumps; 150 µm with solder bumps, 200 µm with gold bumps; 6 in and smaller: 70 µm, or 60 µm on engineering lots; Polish recommended below 150 µm, or 250 µm when bumped - Dicing: Laser dicing, kerf from 20 µm; Blade dicing, kerf from 50 µm; SiC stealth dicing; GaAs laser dicing; MPW and shuttle wafers cut by block, including 5×5; Die or substrate up to 1.0 mm thick - Die sort and handling: Input wafers 3 to 12 in; output to 2–4 in trays or 8 in frames; Sort by ink or wafer map; Die from 180 µm across and 65 µm thick; Tape transfer, including one wafer split across frames; About 15 million die a month; Vacuum anti-static packing - Marking: Laser marking Volume capacity (Wafer | Minimum thickness | Minimum kerf | Wafers a month): - 4 and 5 in | 70 µm | 50 µm | 5,000 each - 6 in | 70 µm | 20 µm laser, 50 µm blade | 5,000 - 8 in | 70 µm; 150 µm solder bump; 200 µm gold bump | 50 µm | 5,000 - 12 in | 75 µm; 150 µm solder bump; 200 µm gold bump | 50 µm; 60 µm bumped | 5,000 FAQ: - Q: Can you dice our die out of an MPW shuttle wafer? A: Yes. MPW and shuttle wafers are cut by block, including 5×5 layouts, and the die are sorted for packaging. - Q: How thin can you go? A: Down to 50 µm on 8 and 12 in wafers without bumps, 150 µm with solder bumps, and 200 µm with gold bumps. - Q: Do you dice SiC and GaAs? A: Yes: stealth dicing for SiC and laser dicing for GaAs. ### How quoting works 1. Send the die details: size, pad count, target package, quantity, and any qualification standard. 2. We confirm feasibility and the bond plan, or come back with the questions that decide it. 3. You get a quote per die and drawing, within 1–2 business days of a complete intake. 4. Parts ship back packaged, and qualification or failure analysis can run on the same lot. ### Your die, your IP - We sign your NDA before you send die, drawings, or GDS, or send you ours. - Your die, files, and test data are used only for your job. - Leftover die and wafers are returned or destroyed, your choice. - [Send us your die](https://www.expertx.net/apply/packaging): Start a packaging, qualification, or failure-analysis engagement. - [Start an engineering project](https://www.expertx.net/apply): Tell us what the board is, what it has to do, and what's already been tried. ## Origination - [Origination overview](https://www.expertx.net/origination): ExpertX originates, structures, and executes large, relationship-dependent B2B deals across construction, energy, manufacturing, semiconductors, defense, and capital markets. Success-fee on what we source, project fees on what we deliver. - [How we work](https://www.expertx.net/origination/how-we-work): Three phases (Originate, Structure, Execute) and an engagement model that splits success-fee and project work plainly. - [Who we work with](https://www.expertx.net/origination/who-we-work-with): Our ideal client profile and the engagements we decline. - [Apply](https://www.expertx.net/origination/apply): Apply for an origination engagement. ## Results - [Packaged a CPU + FPGA network processor in a 61 mm flip-chip BGA with 3,576 balls](https://www.expertx.net/results/multi-die-network-processor-fcbga): A multi-die network processor needed one package to carry its CPU, its FPGA, and their high-speed links. We designed the substrate and built it as a 61 × 61 mm flip-chip BGA with a heat spreader: 3,576 balls on a 10-layer organic substrate. - [Built out a tier-one solar manufacturer's rework team — 100+ workers staffed into the factory](https://www.expertx.net/results/solar-manufacturer-rework-staffing): Stood up the rework operation at a tier-one solar manufacturer in DFW — 100+ workers placed across production, materials, QC, and shipment teams, technical and non-technical roles both, in the weeks the factory needed them. - [Connected a Tier-2 defense contractor with new suppliers — $30M+ in deployed spend](https://www.expertx.net/results/defense-tier2-supplier-network): Opened a fresh supplier base for a Tier-2 defense contractor, structuring vendor relationships that turned into $30M+ in deployed spend over the engagement. - [Onshored a leading chip-design and test firm's engineering team](https://www.expertx.net/results/semiconductor-engineering-onshoring): Restructured the engineering org of a leading chip-design and testing firm — cut offshore dependency in critical paths and built a senior onshore engineering bench to run the work in-house. - [Root-caused a power-sequencing hang on first-spin silicon — pilot shipped on time, no re-spin](https://www.expertx.net/results/soc-power-sequencing-bring-up): A six-rail SoC wouldn't come out of reset on first-spin boards. We scoped the rail sequence, isolated a missing pull-down on the PMIC enable line, applied a wire-mod, and put working prototypes on a customer plane the same week — without a re-spin. ## About - [Principals](https://www.expertx.net/about): Two practices on one bench: an engineering studio led by Khurshid Alam and an origination practice led by Erteza Alam.