Root-caused a power-sequencing hang on first-spin silicon — pilot shipped on time, no re-spin

The situation

A mid-market edge-compute OEM had just received first-spin boards built around a six-rail SoC. The boards weren't coming out of reset cleanly — all rails would reach nominal and assert power-good, then the chip would hang before secondary boot. The vendor's FAE wanted to blame silicon. The customer was a week away from putting prototypes on a plane for a Tier-1 industrial pilot, and the team was staring down a full re-spin that would have pushed the pilot past the customer's quarterly window.

What we did

1. 01

   Scoped the rail sequence on the actual board against the SoC's specified power-up envelope. The captured trace showed every rail reaching nominal, but the PMIC enable line ramping a few hundred microseconds outside the window the SoC expected for clean VID latching.

2. 02

   Traced the timing violation to a single missing pull-down on the PMIC enable line — left floating in the rev-A schematic, the line was being driven by internal leakage rather than a defined resistor, so it sat at an undefined level during the regulator startup ramp and the chip latched against the wrong sequence.

3. 03

   Applied a wire-mod on the prototype to add the missing pull-down, validated against a full boot cycle and a thermal soak across the operating range, and redlined the schematic for rev-B so the fix rolls into volume without anyone having to remember it again.

Outcome

Prototypes shipped to the customer site on the original schedule. The pilot ran with hardware identical to what production will see. No re-spin, no chip swap, no customer reschedule — three days from boards-back to working units in the field.