Engineering · 05 · Package & Test
Packaging, Test & Failure Analysis
Quick-turn packaging, reliability qualification, and failure analysis built for NPI: one team from first silicon to a qualified part on a working board.
What it is
New product introduction is where packaging, test, and board design usually live with three different vendors, and the schedule dies in the handoffs between them. We run all three on one team. Die comes in, gets packaged, qualified, and debugged, and lands on a board we designed for it, without anyone re-explaining the part at each step.
Silicon has to get into a package before it can go on a board, and that step is where small-batch programs stall. Engineering samples, MPW shuttle die, and MEMS parts rarely justify a production slot at a large assembly house, but they still need the right package on a schedule measured in days, not quarters.
We cover the post-fab path at prototype and small-batch volumes: wafer thinning and dicing, quick-turn ceramic and plastic packaging, reliability qualification, electrical test, and failure analysis when a part doesn't behave. Because the board team is in the room, the package gets picked with the footprint, thermals, and assembly already in view.
Capabilities
- Quick-turn packaging
- Ceramic: DIP, QFP, SOP, QFN, LCC, PGA, SiP, BGA
- Plastic: DIP, LQFP, QFN, DFN, SOP, SSOP, TSSOP, SOT, TO, BGA
- Chip-on-board (COB) bonding
- BGA, LGA, and multi-die stacked packages
- MEMS sensor and optical device packages
- LCD driver IC bonding
- Wafer services
- MPW and shuttle die handling, block and 5×5
- 6 to 12 inch wafer thinning and dicing
- GaAs thinning and dicing
- Automated bare-die pick and sort, vacuum packing
- Substrates
- High-speed BGA substrate design and simulation
- Substrate fabrication and processing
- Reliability qualification
- HTOL, HTRB, HTGB, H3TRB
- THB, HAST, PCT, TCT, THST, THCT
- HTST, LTST, BLT
- MSL preconditioning and reflow
- Burn-in boards and DUT cards
- Electrical test
- ESD: HBM, MM, CDM
- Latch-up
- Wafer probe (CP) and final test (FT)
- Failure analysis & circuit edit
- FIB circuit edit down to 28nm
- Chemical and physical decap, die extraction, delayering
- SEM imaging from 50× to 200,000×
- Backside FA sample prep and defect localization
- Competitive teardown analysis
- Rework & custom hardware
- Post-decap re-bonding, wire removal, and jumpers
- BGA reballing, re-soldering, dispensing, and molding
- MEMS housings with windows and special ceramic packages
- Custom test fixtures
Plastic package catalog
Standard quick-turn plastic packages, small batch. Bring the die and the target package and we'll confirm the bond plan.
| Package | Pins | Body size |
|---|---|---|
| LQFP | 32–256 | 5×5 to 28×28 mm |
| eLQFP / HLQFP (heat slug) | 80, 128, 144, 176 | 12×12 to 20×20 mm |
| QFN | 12–100 | 2×2 to 10×10 mm, 12×18 mm |
| DFN | 8–16 | 2×3 to 5×6 mm |
| DIP | 8–48 | Standard |
| SOP | 8–32 | Standard |
| SSOP | 8–28 | Standard |
| TSSOP | 8–30 | Standard |
| eSOP | 8, 10, 28 | Standard |
| MSOP | 8, 10 | Standard |
| SOT | 3, 5, 6 | Standard |
| TO | 90, 94, 220, 247, 251, 252, 263 | Standard |
Ceramic, COB, BGA, LGA, and MEMS packages are quoted per die and drawing.
Quality systems
ISO 9001
Quality management
ISO 14001
Environmental management
ISO 45001
Occupational health & safety
Packaging and test performed in ISO 9001, ISO 14001, and ISO 45001-certified facilities. Certificates available under NDA.
Often paired with
Hardware Engineering
Board-level design for systems where signal integrity, power, and thermals are non-negotiable.
Firmware & Embedded Systems
Bare-metal and RTOS firmware on ARM, RISC-V, and Espressif — from board bring-up to OTA.
PCB Design & Layout
Two to seventy-six layers, including HDI, flex, rigid-flex, and high-speed — with SI/PI built into the routing, not bolted on at the end.
Manufacturing & Assembly
Prototype to production, SMT and through-hole, with sourcing and quality systems in the same engagement.