Network-processor program · Networking silicon · Packaging · Substrate design
Packaged a CPU + FPGA network processor in a 61 mm flip-chip BGA with 3,576 balls
A multi-die network processor needed one package to carry its CPU, its FPGA, and their high-speed links. We designed the substrate and built it as a 61 × 61 mm flip-chip BGA with a heat spreader: 3,576 balls on a 10-layer organic substrate.
3,576
solder balls on a 61 × 61 mm flip-chip BGA, 10-layer substrate
The situation
The design put a CPU and an FPGA in a single multi-chip package, with DDR3 at 1,600 Mbps, PCIe 2.0 at 5 Gbps, and XAUI at 6.25 Gbps all running through it. At a 61 × 61 ball array, the substrate was as much a design problem as the die: stack-up, routing, power delivery, and heat had to work together in one package.
What we did
- 01
Chose a flip-chip BGA with an integrated heat spreader (HFcBGA), so both die could be flip-chip mounted and the CPU and FPGA could shed heat through one lid.
- 02
Designed the 10-layer organic substrate and the 3,576-ball map, routing the DDR3, PCIe 2.0, and XAUI interfaces through the stack-up.
- 03
Ran the package through chip-package-substrate co-simulation, covering signal integrity, power integrity, thermal behavior, and structural stress.
Outcome
Built as a 61 × 61 mm HFcBGA: 3,576 balls on a 10-layer organic substrate, carrying DDR3 at 1,600 Mbps, PCIe 2.0 at 5 Gbps, and XAUI at 6.25 Gbps in one multi-die package.