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Packaging & Test · Design

Package & Substrate Design

Package selection, substrate stack-up, ball maps, and SI, PI, and thermal co-simulation for flip-chip BGA, SiP, and chiplet designs.

What it is

Above a few hundred balls, the package stops being a container and becomes a circuit. Stack-up, ball map, and power delivery decide whether the DDR and SerDes links close, and they're cheapest to fix before the substrate is built.

We design the package and substrate alongside the die and the board: package and material selection, stack-up, ball map, impedance, and substrate layout, checked with chip-package-substrate co-simulation. The same team designs the board it lands on, so the ball map is planned against the breakout.

Inside a SiP

A system-in-package in section: a flip-chip die, a wire-bonded die stack, and passives on one substrate, molded as a single part.

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  1. 1Flip-chip dieBumped face down onto the substrate
  2. 2Stacked dieTwo die, wire-bonded in one footprint
  3. 3PassivesSMT capacitors and resistors inside the package
  4. 4Mold compoundOne molded body over everything
  5. 5SubstrateRoutes every die to the ball array
  6. 6Solder ballsOne BGA footprint on the board

Capabilities

Custom design
  • Package selection
  • Substrate and material selection
  • Stack-up and ball-map design
  • Impedance design
  • Substrate layout
Simulation
  • Power and ground, DC and AC
  • High-speed and system-level channel simulation
  • Thermal performance
  • Structural design and stress
  • EMI, SI, and PI co-optimization
Advanced integration
  • System-in-package: side by side, stacked die, IC plus passives
  • Wire bond, flip chip, and SMT in one package
  • TSV 2.5D interposer design
  • Chiplet-based micro-systems and heterogeneous integration
  • DDR3 and Flash wafer-level packaging with bumping
Substrates
  • High-speed BGA substrate design and fabrication
  • Organic substrates, BT and ABF build-up
  • Multilayer ceramic substrates

Representative builds

Packages designed and built on our bench, client details removed.

BuildPackage and substrateSize and ballsKey interfaces
CPU + FPGA network processorHFcBGA, 10-layer organic61×61 mm, 3,576 ballsDDR3 1,600 Mbps, PCIe 2.0, XAUI 6.25 Gbps
CPU + FPGA + Flash SiPHFcBGA, 10-layer organic50×50 mm, 2,089 ballsPCIe x16 3.0, DDR3 x72, USB 2.0
Integrated DSP moduleHFcBGA, 10-layer organic35×35 mm, 1,024 balls4×72-bit DDR3, PCIe 3.0, 10.125 Gbps SerDes, 60 W, 8 GB DDR4 inside
AI chip for healthcarefcBGA, 10-layer organic23×23 mm, 529 ballsLPDDR4 at 4,266 MHz
Fibre Channel switchfcBGA, 6-layer organic19×19 mm, 529 ballsMultiple 12.5 Gbps SerDes
Mixed-signal RF transceiver SoCfcBGA, 8-layer ABF build-up15×15 mm, 289 balls16 Gbps SerDes, 1.5 GHz ADC input
AD/DA SiPBGA, 6-layer BT27×27 mm, 636 balls3-tier gold-wire fan-out, 1 digital + 4 ADC + 1 DAC + Flash
Health-monitoring SiPPackage-on-package, 4-layer organic18×18 mm, 393 ballsCopper-core-ball interposer, several mixed-signal die

Quality systems

  • ISO 9001

    Quality management

  • ISO 14001

    Environmental management

  • ISO 45001

    Occupational health & safety

Packaging and test performed in ISO 9001, ISO 14001, and ISO 45001-certified facilities. Certificates available under NDA.

Common questions

Can you design the substrate if we only have the die?
Yes. Package selection, stack-up, ball map, and substrate layout start from the die pad map and the board it has to land on.
Do you simulate before the substrate is built?
Yes. Chip, package, and substrate are co-simulated for signal integrity, power integrity, thermal behavior, and structural stress.
Do you do SiP and chiplet designs?
Yes: side-by-side and stacked-die SiP, IC plus passives, mixed wire bond, flip chip, and SMT, plus TSV 2.5D interposer and chiplet-based designs.

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