Packaging & Test · Ceramic
Quick-Turn Ceramic Packaging
Small-batch ceramic DIP, QFP, QFN, LCC, PGA, SiP, and BGA packages for engineering samples, MPW die, and parts that need to survive characterization.
What it is
Ceramic is the default for first silicon that has to be characterized hard: it runs hotter, seals better, and opens cleanly when a part needs to come back out for failure analysis. The catch is that production ceramic lines aren't set up for twenty parts.
We package ceramic in small batches, from a handful of MPW die to a pilot lot, and quote per die and drawing. Cavity, lid, bond plan, and pinout are worked out against the board the part is going onto, so the first package is one the board team can actually use.
Inside the package
An open-cavity ceramic package in section: the die sits in a cavity, wires run to a bond shelf, and a seam-sealed lid closes it.
- 1LidMetal lid, seam-sealed over the cavity
- 2Seal ringMetallized ring the lid is welded to
- 3Bond wiresFine wire from die pads to the shelf
- 4DieAttached to the cavity floor
- 5Bond shelfPads routed through the ceramic to the leads
- 6Ceramic bodyMultilayer ceramic, sealed once lidded
- 7LeadsCarry the signals out to the board
Capabilities
- Package families
- Ceramic DIP and SOP
- Ceramic QFP and QFN
- LCC (leadless chip carrier)
- PGA (pin grid array)
- Ceramic BGA and SiP
- Specialty builds
- Chip-on-board (COB) bonding
- Multi-die stacked packages
- MEMS sensor and optical packages, including housings with windows
- Special and custom ceramic packages to drawing
- LCD driver IC bonding
- Wafer prep in the same flow
- MPW and shuttle die handling, block and 5×5
- Wafer thinning and dicing, including GaAs
- Automated bare-die pick and sort
Ceramic & COB catalog
Quick-turn ceramic and chip-on-board packages, small batch. Ceramic BGA and special cavities are built to drawing.
| Package | Pins | Body size |
|---|---|---|
| Ceramic QFP | 64–256 | 10×10 to 28×28 mm |
| Ceramic DIP | 8–64 | 300, 600, 900 mil |
| Open-cavity QFN | 16–100 | 2×2 to 12×12 mm |
| Ceramic SOP | 16, 24 | Standard |
| Ceramic PGA | 84, 100, 132, 256 | Standard |
| Ceramic LCC | 28, 48, 64, 84 | Standard |
| Ceramic BGA | To drawing | To drawing |
| COB | 48, 64, 256, 1,024, or to drawing | To drawing |
Lids can be parallel seam welded; MEMS housings can take an optical or open window.
Quality systems
ISO 9001
Quality management
ISO 14001
Environmental management
ISO 45001
Occupational health & safety
Packaging and test performed in ISO 9001, ISO 14001, and ISO 45001-certified facilities. Certificates available under NDA.
Common questions
- What's the minimum quantity for ceramic packaging?
- There isn't a production-style minimum. Ceramic builds are quoted per die and drawing, and engineering-sample quantities are the normal case.
- Can you package die from an MPW shuttle?
- Yes. We handle MPW and shuttle die, including block and 5×5 formats, and can thin, dice, and sort before packaging.
- When should I pick ceramic over plastic for first silicon?
- Ceramic suits characterization at temperature, hermetic needs, and parts likely to need decap and failure analysis. Plastic is closer to the production package and cheaper per unit. Many NPI programs do both.
More packaging & test
Packaging, Test & Failure Analysis
Quick-turn packaging, reliability qualification, and failure analysis built for NPI: one team from first silicon to a qualified part on a working board.
Quick-Turn Plastic Packaging
Small-batch molded packages from 3-pin SOT to 256-pin LQFP, so engineering samples ship in the package production will use.
Reliability Qualification & Electrical Test
HTOL, HAST, THB, temperature cycling, ESD, and latch-up for new parts, plus the burn-in boards and DUT cards to run them.
Failure Analysis & FIB Circuit Edit
FIB circuit edit down to 28nm, decap, delayering, and SEM imaging, so a first-silicon bug can be proven and patched before the next tape-out.
Package & Substrate Design
Package selection, substrate stack-up, ball maps, and SI, PI, and thermal co-simulation for flip-chip BGA, SiP, and chiplet designs.
Wafer Thinning, Dicing & Die Sort
Thinning to 50 µm, laser and blade dicing, SiC stealth dicing, GaAs laser dicing, and automated die sort for MPW, shuttle, and full wafers.