Packaging & Test · Failure analysis
Failure Analysis & FIB Circuit Edit
FIB circuit edit down to 28nm, decap, delayering, and SEM imaging, so a first-silicon bug can be proven and patched before the next tape-out.
What it is
When first silicon doesn't behave, the expensive question is whether the fix needs a new mask set. FIB circuit edit answers it: cut and reroute metal on the actual die, prove the fix on the bench, and only then commit to a re-spin.
Failure analysis runs alongside it. We decap, delayer, and image down to the defect, and because the same team packaged the part and designed the board, the analysis starts with the full history instead of a box of returned units.
How a circuit edit works
A FIB edit in section: the beam cuts the old path, then gas-assisted deposition lays a platinum jumper to make the new one.
- 1Focused ion beamMills and images at nanometer scale
- 2Gas injectionFeeds the precursor for deposition
- 3CutSevers the metal line to open the old path
- 4Platinum jumperDeposited line that makes the new connection
- 5ContactsMilled down to the metal, then filled
- 6PassivationOpened only where the edit needs it
From a failing part to the root cause
- 01LocalizePhoton emission finds the hot spot
- 02Cross-sectionFIB cuts through the exact site
- 03AnalyzeSEM imaging and EDX composition
Capabilities
- Circuit edit
- FIB circuit edit down to the 28nm node
- Metal cuts and reroutes on the actual die
- Failure analysis
- Chemical and physical decap
- Die extraction and delayering
- SEM imaging from 50× to 200,000×
- Backside FA sample prep
- Hot-spot localization by photon emission (EMMI)
- Cross-sections, TEM sample prep, voltage contrast
- Remarking
- Post-decap rework
- Re-bonding, wire removal, and jumpers
- Re-soldering and BGA reballing
- Dispensing and re-molding
- Competitive analysis
- Teardown and construction analysis of third-party parts
FIB metal resistance
FIB-deposited metal resists more than CVD or bulk metal, and contacts more than lines. Rewires are sized to keep the deposited line under 10 Ω.
| Metal | Bulk | CVD | FIB line | FIB contact |
|---|---|---|---|---|
| Tungsten (W) | 0.05 | 0.2 | 3 | 70 |
| Platinum (Pt) | 0.1 | 0.5 | 7 | 140 |
Resistivity in Ω·µm.
Quality systems
ISO 9001
Quality management
ISO 14001
Environmental management
ISO 45001
Occupational health & safety
Packaging and test performed in ISO 9001, ISO 14001, and ISO 45001-certified facilities. Certificates available under NDA.
Common questions
- What's the smallest node you can FIB edit?
- Circuit edit is supported down to the 28nm node.
- Can you rebond or repackage a part after decap?
- Yes. Post-decap rework covers re-bonding, wire removal, jumpers, re-soldering, BGA reballing, dispensing, and re-molding.
- Do you do competitive teardown?
- Yes. Teardown and construction analysis of third-party parts is part of the failure-analysis practice.
More packaging & test
Packaging, Test & Failure Analysis
Quick-turn packaging, reliability qualification, and failure analysis built for NPI: one team from first silicon to a qualified part on a working board.
Quick-Turn Ceramic Packaging
Small-batch ceramic DIP, QFP, QFN, LCC, PGA, SiP, and BGA packages for engineering samples, MPW die, and parts that need to survive characterization.
Quick-Turn Plastic Packaging
Small-batch molded packages from 3-pin SOT to 256-pin LQFP, so engineering samples ship in the package production will use.
Reliability Qualification & Electrical Test
HTOL, HAST, THB, temperature cycling, ESD, and latch-up for new parts, plus the burn-in boards and DUT cards to run them.
Package & Substrate Design
Package selection, substrate stack-up, ball maps, and SI, PI, and thermal co-simulation for flip-chip BGA, SiP, and chiplet designs.
Wafer Thinning, Dicing & Die Sort
Thinning to 50 µm, laser and blade dicing, SiC stealth dicing, GaAs laser dicing, and automated die sort for MPW, shuttle, and full wafers.